Page 332 Friday, January 18, 2002 9:09 AM in Microsoft Office Access data matrix barcodes in Microsoft Office Page 332 Friday, January 18, 2002 9:09 AM Page 332 Friday, January 18, 2002 9:09 AM using barcode drawer for microsoft control to generate, create barcode data matrix image in microsoft applications. USD8 DESIGNING SEQUENTIAL LOGIC CIRCUITS 7 . Vout In VOL (b) Schematic symbol VM VM+ DataMatrix for None Vin (a) Voltage-transfer characteristic Figure 7.46 Non-inverting Schmitt trigger..

CMOS Implementation One possi ble CMOS implementation of the Schmitt trigger is shown in Figure 7.48. The idea behind this circuit is that the switching threshold of a CMOS inverter is determined by the (kn/kp) ratio between the NMOS and PMOS transistors.

Increasing the ratio results in a reduction of the threshold, while decreasing it results in an increase in VM. Adapting the ratio depending upon the direction of the transition results in a shift in the switching threshold and a hysteresis effect. This adaptation is achieved with the aid of feedback.

Suppose that Vin is initially equal to 0, so that Vout = 0 as well. The feedback loop biases the PMOS transistor M4 in the conductive mode while M3 is off. The input signal effectively connects to an inverter consisting of two PMOS transistors in parallel (M2 and M4) as a pull-up network, and a single NMOS transistor (M1) in the pull-down chain.

This modifies the effective transistor ratio of the inverter to kM1/(kM2+kM4), which moves the switching threshold upwards. Once the inverter switches, the feedback loop turns off M4, and the NMOS device M3 is activated. This extra pull-down device speeds up the transition and produces a clean output signal with steep slopes.

A similar behavior can be observed for the high-to-low transition. In this case, the pull-down network originally consists of M1 and M3 in parallel, while the pull-up network is formed by M2. This reduces the value of the switching threshold to VM .

. Vin Vout t0 Figure 7.47 t Noise suppression using a Schmitt trigger. t0 + tp Page 333 Friday, January 18, 2002 9:09 AM Section 7.6 Non-Bistable Sequential Circuits M2 Vin X M4 Vout CMOS Schmitt trigger. Example 7.7 CMOS Schmitt Trigger Consider the schmitt trigger Microsoft Office DataMatrix with the following device sizes. Devices M1 and M2 are 1 m/0.25 m, and 3 m/0.

25 m, respectively. The inverter is sized such that the switching threshold is around VDD/2 (= 1.25 V).

Figure 7.49a shows the simulation of the Schmitt trigger assuming that devices M3 and M4 are 0.5 m/0.

25 m and 1.5 m/0.25 m, respectively.

As apparent from the plot, the circuit exhibits hysteresis. The high-to-low switching point (VM- = 0.9 V) is lower than VDD/2, while the low-to-high switching threshold (VM+ = 1.

6 V) is larger than VDD/2.. VX (V). VM+ VMVx (V). 1.0 k=1 k=3 k=4 0.0 0.0.

1.5 Vin(V). 0.0 0.0.

Vin(V). (a) Voltage-transfer characteristics with hysteresis. Figure 7.49 Schmitt trigger simulations. (b) The effect of varying the ratio of the PMOS device M4. The width is k * 0.5 m. It is possible to shift the s Data Matrix 2d barcode for None witching point by changing the sizes of M3 and M4. For example, to modify the low-to-high transition, we need to vary the PMOS device. The highto-low threshold is kept constant by keeping the device width of M3 at 0.

5 m. The device width of M4 is varied as k * 0.5 m.

Figure 7.49b demonstrates how the switching threshold increases with raising values of k.. Page 334 Friday, January 18, 2002 9:09 AM DESIGNING SEQUENTIAL LOGIC CIRCUITS 7 . Problem 7.8 An Alternative CMOS Schmitt Trigger Another CMOS Schmitt trigger Microsoft DataMatrix is shown in Figure 7.50. Discuss the operation of the gate, and derive expressions for VM and VM+.

. VDD M4 M6 M3 In M2 X M1 Figure 7.50 Alternate CMOS Schmitt trigger. M5 VDD Out Monostable Sequential Circuits A monostable element is a cir cuit that generates a pulse of a predetermined width every time the quiescent circuit is triggered by a pulse or transition event. It is called monostable because it has only one stable state (the quiescent one). A trigger event, which is either a signal transition or a pulse, causes the circuit to go temporarily into another quasi-stable state.

This means that it eventually returns to its original state after a time period determined by the circuit parameters. This circuit, also called a one-shot, is useful in generating pulses of a known length. This functionality is required in a wide range of applications.

We have already seen the use of a one-shot in the construction of glitch registers. Another notorious example is the address transition detection (ATD) circuit, used for the timing generation in static memories. This circuit detects a change in a signal, or group of signals, such as the address or data bus, and produces a pulse to initialize the subsequent circuitry.

The most common approach to the implementation of one-shots is the use of a simple delay element to control the duration of the pulse. The concept is illustrated in Figure 7.51.

In the quiescent state, both inputs to the XOR are identical, and the output is low. A transition on the input causes the XOR inputs to differ temporarily and the output to go high. After a delay td (of the delay element), this disruption is removed, and the output goes low again.

A pulse of length td is created. The delay circuit can be realized in many different ways, such as an RC-network or a chain of basic gates..

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